This invention relates to a data output buffer of a static random access memory (SRAM) and more particularly to a data output buffer of SRAM with a high impedance output driver stage.
Recently, there have been design approaches for higher speed and for lower power consumption of the SRAM. According to this tendency, in making a SRAM, the delay time of the data output buffer matters in the portion of the access time of the memory. However, there is a bad influence resulting from earthed voltage noise (V.sub.SS Noise) or V.sub.CC Noise (Power Supply Voltage Noise) by the peak current at the time of reading data of two opposite states sequentially more than twice, i.e., the voltage of input-output being changed from high to low or from low to high.
FIG. 1 shows a schematic diagram of a data output buffer in a general SRAM. At first, the output SAS, SAS of a sensing amplifier SA which differentially amplifies data of bit lines BL, BL are equalized with the middle level between low and high state, and then they are split to the state of high or low according to the data of the bit lines BL, BL which perceive a memory cell. Then, data are offered through a data buffer DB controlled by a read-write control buffer R/WB.
FIG. 2 shows the circuit diagram of a conventional data output buffer. The output SAS of a sense amplifier and the single pulse out signal .phi..sub.PZ3 of a single pulse generator which is combinating short pulses resulting from transition of external address signals, are connected to the input terminal of a NAND gate NA.sub.1, and the output terminal of said signal pulse generator .phi..sub.PZ3 is connected to the gate of a NMOS transistor T.sub.21 and a inverter N.sub.3.
The output terminal of said inverter N.sub.3 is connected to the gate of a PMOS transistor T.sub.20 and the drains of said PMOS transistor T.sub.20 and NMOS transistor T.sub.21 are connected to the output terminal of said NAND gate NA.sub.1.
A latch composed of inverters N.sub.1, N.sub.2 is connected to the source of the transistors T.sub.20, T.sub.21, and the output terminal of the inverter N.sub.1 is connected to input terminals of a NAND gate NA.sub.2 and NOR gate NO.sub.1, respectively. And the output signal OE of the read/write control buffer R/WB is inputted to the NOR gate NO.sub.1, and the NAND gate NA.sub.2 through the inverter N.sub.9. The output terminal 50 of the NOR gate NO.sub.1 is connected to the inverters N.sub.6, N.sub.8, and the output terminal 40 of the NAND gate NA.sub.2 is connected to inverters N.sub.4, N.sub.7.
The output terminal 70 of the inverter N.sub.8 is connected to the gate of a NMOS transistor T.sub.2 ; the output terminal 60 of the inverter N.sub.7 is connected to a PMOS transistor T.sub.22 ; the drain of said PMOS transistor T.sub.22 is connected to the power supply V.sub.CC ; the source of said NMOS transistor T.sub.23 is grounded, and the source of the PMOS transistor T.sub.22 and the drain of the NMOS transistor T.sub.23 are connected at point 80 point 80 is connected to the data input-output terminal.
FIG. 3 shows the operational waveforms of FIG. 2, in which:
3a shows the output signal SAS of the sense amplifier SA, PA1 3b shows the single pulse output signal .phi..sub.PZ3, PA1 3c shows the output signal of the NAND gate NA.sub.1, PA1 3d shows the signal at the input terminal 20 of the inverter N.sub.1, PA1 3e shows the output signal at the output terminal 30 of the inverter N.sub.1, PA1 3f shows the output signal at the output terminal 40 of the NAND gate NA.sub.2, PA1 3g shows the output signal at the output terminal 60 of the inverter N.sub.7, PA1 3h shows the output signal at the output terminal 50 of the NOR gate NO.sub.1, PA1 3i shows the output signal at the output terminal 70 of the inverter N.sub.8, and PA1 3j shows the output signal of the output drive terminal 80.
The operation of the conventional data output buffer is described below with reference to FIG. 2 and FIG. 3.
During a read cycle, the output enable signal OE is low, and the output signal SAS of the sense amplifier SA is equalized with the middle level between the high and low level. If there are data which come from the memory cell, the state becomes high or low level. When the output signal SAS of the sense amplifier SA is an enough high level like the waveform as shown in FIG. 3a, the single pulse output signal .phi..sub.PZ3 goes to a high state for a given moment.
When a single pulse output .phi..sub.PZ3 is transmitted to high, the output signal at output terminal 10 of the NAND gate NA.sub.1 goes to a low state as shown in FIG. 3c, and this signal goes to a high state when .phi..sub.PZ3 is low. Then the control signal 3b of the single pulse output signal .phi..sub.PZ3 switches the P, N MOS transistors T.sub.20, T.sub.21, and the output of node 20 goes to a low state. This signal is latched in the latch circuit composed of the two inverters N.sub.1, N.sub.2. Because said output enable signal OE is in a low state, the output of the inverter N.sub.9 goes to high state and this signal is inputted to the NAND gate NA.sub.2 with the signal shown by FIG. 3e.
The output signal waveform at the output terminal 40 of the NAND gate NA.sub.2 is shown in FIG. 3f. Through the inverters N.sub.4, N.sub.7, this signal goes to a low output state and this output turns on the PMOS transistor T.sub.22. The output of the NOR gate NO.sub.1 is at a low state as shown in FIG. 3e, and through the inverters N.sub.6, N.sub.8, this signal goes to a low state as shown in FIG. 3i. Finally the NMOS transistor T.sub.23 becomes off and the output at the node 80 becomes a high state as shown in FIG. 3j.
Since said data output buffer circuit has a complex composition because of the multiplicity of gates, and the signal trip time from the sense amplifier SA to the driver output terminal 80 is so long that the speed is reduced.
As a property of the memory, general output driver transistors T.sub.22. T.sub.23 are large in size. Because of that size, peak currents resulted from the direct current path which is broken out in transistions of outputs cause a problem of V.sub.CC Noise and V.sub.SS Noise.